The present invention relates to semiconductor devices which include a plurality of memory macros each having a plurality of memory cells.
Semiconductor devices have been continuously achieving higher performance and greater functionality. Development of system LSIs, in which various kinds of function blocks each having a specific function are mounted on a single chip so that the single chip realizes a highly sophisticated function, has been rapidly proceeding today.
FIG. 12 is a block diagram illustrating an exemplary configuration of a conventional semiconductor device. The semiconductor device 900 of FIG. 12 is a system LSI and includes memory macros 911, 912, 913, and 914 and a memory macro control circuit 930.
Control signals ZI are input to the memory macro control circuit 930 from a device external to the semiconductor device 900. Via an all-macro common signal bus which transmits common signals to all of the memory macros, the memory macro control circuit 930 outputs an all-macro common signal ZA to the memory macros 911 through 914. The memory macro control circuit 930 also outputs active-macro selection signals ZB1, ZB2, ZB3, and ZB4 that correspond to the respective memory macros 911 through 914 and activate the corresponding memory macros 911 through 914.
The all-macro common signal ZA contains an address signal for selecting a specific memory cell within each memory macro, a read/write operation control signal, write-in data and the like. Although a read-out data bus for transmitting data read out from the memory macros and various kinds of other function blocks are incorporated in the semiconductor device 900, illustration of those members is omitted in FIG. 12.
Hereinafter, it will be explained how the conventional semiconductor device 900 configured in this manner operates. The memory macro control circuit 930 is controlled by the control signals ZI, and generates the signals in the all-macro common signal ZA and the active-macro selection signals ZB1 through ZB4 so as to activate a specific one of the memory macros 911 through 914.
The all-macro common signal, which is common to all of the memory macros, is transmitted by the all-macro common signal bus. At the same time, for example, in a case where the memory macro 911 is activated, only the active-macro selection signal ZB1 of the active-macro selection signals ZB1 through ZB4 goes to the “H” level, while the active-macro selection signals ZB2 through ZB4 go to the “L” level (“H” and “L” indicate logical states.)
Each memory macro accepts the all-macro common signal only when the input active-macro selection signal is at the “H” level. In this case, only the memory macro 911 accepts the all-macro common signal and operates, while the other memory macros 912 through 914 do not operate even if the all-macro common signal is input to them. In cases where another memory macro is activated, only one of the memory macros operates as in the case of the memory macro 911.
As described above, in the semiconductor device 900, two or more of the memory macros are not activated at the same time, and only one of them is activated.
A related technique is disclosed in Japanese Laid-Open Publication No. 11-231023.
However, if a semiconductor device incorporating a plurality of memory macros is designed so that only one of the memory macros is activated, the memory macros have to be activated one by one in order to activate all of the memory macros. Therefore, a problem is caused in that as the number of memory macros incorporated into the semiconductor device rises, time required for a test or the like, such as time required for a burn-in process for removing initial degradation, a non-defective item selecting process, and a reliability evaluation process, also increases.